Systems and methods for performing matrix compress and decompress instructions
US-2025199812-A1 · Jun 19, 2025 · US
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Espig Michael patents
Espig Michael is listed as an inventor on 49 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Espig Michael |
| Total patents | 49 |
| First publication | Feb 7, 2019 |
| Latest publication | Jun 19, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Compressed wallace trees in FMA circuits
US-12321714-B2 · Jun 3, 2025 · US
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
US-12287843-B2 · Apr 29, 2025 · US
Zero-clearing scalar moves
US-2025028533-A1 · Jan 23, 2025 · US
Support for less than 512-bit operand processing
US-2025004764-A1 · Jan 2, 2025 · US
Apparatuses, methods, and systems for a packed data convolution instruction with shift control and width control
US-12182570-B2 · Dec 31, 2024 · US
Systems and methods for performing matrix compress and decompress instructions
US-12175246-B2 · Dec 24, 2024 · US
Instruction and logic for sum of square differences
US-12099838-B2 · Sep 24, 2024 · US
Restricting vector length in a processor
US-2024220248-A1 · Jul 4, 2024 · US
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
US-2024078285-A1 · Mar 7, 2024 · US
Recent patents
Latest publications not already listed above.
Systems and methods for performing matrix compress and decompress instructions
US-2024045690-A1 · Feb 8, 2024 · US
Systems and methods for performing nibble-sized operations on matrix elements
US-11886875-B2 · Jan 30, 2024 · US
Vector unpack based on selection information
US-2024004648-A1 · Jan 4, 2024 · US
Instructions and support for horizontal reductions
US-2024004662-A1 · Jan 4, 2024 · US
Systems and methods of instructions to accelerate multiplication of sparse matrices using bitmasks that identify non-zero elements
US-11847185-B2 · Dec 19, 2023 · US
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
US-11836464-B2 · Dec 5, 2023 · US
Systems and methods for performing matrix compress and decompress instructions
US-11748103-B2 · Sep 5, 2023 · US
Method and apparatus for separable convolution filter operations on matrix multiplication arrays
US-2023185873-A1 · Jun 15, 2023 · US
Application negotiable platform thermal aware scheduler
US-2023161941-A1 · May 25, 2023 · US
Apparatuses, methods, and systems for a packed data convolution instruction with shift control and width control
US-2022413853-A1 · Dec 29, 2022 · US
Systems for performing instructions for fast element unpacking into 2-dimensional registers
US-11507376-B2 · Nov 22, 2022 · US
Compressed wallace trees in fma circuits
US-2022365751-A1 · Nov 17, 2022 · US
Method and apparatus for efficient binary and ternary support in fused multiply-add (fma) circuits
US-2022342641-A1 · Oct 27, 2022 · US
Instruction and logic for sum of absolute differences
US-2022308881-A1 · Sep 29, 2022 · US
Instruction and logic for sum of square differences
US-2022197635-A1 · Jun 23, 2022 · US
Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
US-11366636-B2 · Jun 21, 2022 · US
Systems and methods for performing matrix compress and decompress instructions
US-2022171627-A1 · Jun 2, 2022 · US
Method and apparatus for approximation using polynomials
US-11327754-B2 · May 10, 2022 · US
Systems and methods for performing duplicate detection instructions on 2D data
US-11294671-B2 · Apr 5, 2022 · US
Systems and methods for performing matrix compress and decompress instructions
US-11249761-B2 · Feb 15, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 47 |
| Espig Michael | 2 |
| Toll Bret | 2 |
| Sade Raanan | 2 |
| Valentine Robert | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/30036 | 34 |
| G06F9/30038 | 30 |
| G06F17/16 | 25 |
| G06F9/3001 | 22 |
| G06F9/3016 | 20 |