Data scaling
US-2025355622-A1 · Nov 20, 2025 · US
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Chung Eric patents
Chung Eric is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chung Eric |
| Total patents | 27 |
| First publication | Apr 19, 2016 |
| Latest publication | Nov 20, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
System for training an artificial neural network
US-12190235-B2 · Jan 7, 2025 · US
Systems and methods for accelerating the computation of the reciprocal function and the reciprocal-square-root function
US-2023161554-A1 · May 25, 2023 · US
System for training an artificial neural network
US-2022245444-A1 · Aug 4, 2022 · US
Convolutional neural networks on hardware accelerators
US-11200486-B2 · Dec 14, 2021 · US
Customized integrated circuit for serial comparison of nucleotide sequences
US-10566076-B2 · Feb 18, 2020 · US
Deep neural network processing on hardware accelerators with stacked memory
US-10540588-B2 · Jan 21, 2020 · US
Deep neural network partitioning on servers
US-10452971-B2 · Oct 22, 2019 · US
Machine learning classification on hardware accelerators with stacked memory
US-10452995-B2 · Oct 22, 2019 · US
Lightweight transport protocol
US-10455061-B2 · Oct 22, 2019 · US
Recent patents
Latest publications not already listed above.
Convolutional neural networks on hardware accelerators
US-2019311253-A1 · Oct 10, 2019 · US
Reduced memory nucleotide sequence comparison
US-10241970-B2 · Mar 26, 2019 · US
In-line network accelerator
US-10129153-B2 · Nov 13, 2018 · US
Reduced Memory Nucleotide Sequence Comparison
US-2018137085-A1 · May 17, 2018 · US
Lightweight transport protocol
US-2018139310-A1 · May 17, 2018 · US
Customized Integrated Circuit For Serial Performance Of Smith Waterman Analysis
US-2018137237-A1 · May 17, 2018 · US
Lightweight transport protocol
US-9888095-B2 · Feb 6, 2018 · US
In-line network accelerator
US-2017250914-A1 · Aug 31, 2017 · US
In-line network accelerator
US-9674090-B2 · Jun 6, 2017 · US
Machine learning classification on hardware accelerators with stacked memory
US-2016379137-A1 · Dec 29, 2016 · US
In-line network accelerator
US-2016380896-A1 · Dec 29, 2016 · US
Deep neural network partitioning on servers
US-2016379108-A1 · Dec 29, 2016 · US
Deep neural network processing on hardware accelerators with stacked memory
US-2016379115-A1 · Dec 29, 2016 · US
Convolutional neural networks on hardware accelerators
US-2016379109-A1 · Dec 29, 2016 · US
Lightweight transport protocol
US-2016381189-A1 · Dec 29, 2016 · US
Server systems with hardware accelerators including stacked memory
US-2016379686-A1 · Dec 29, 2016 · US
Universal FPGA/ASIC matrix-vector multiplication architecture
US-9317482-B2 · Apr 19, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Microsoft Technology Licensing Llc | 26 |
| Microsoft Corp | 1 |
| Nvidia Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06N3/063 | 10 |
| G06N3/04 | 7 |
| G06N3/045 | 5 |
| G06N3/0464 | 5 |
| G06F15/7803 | 5 |