Shunting networks for access lines in a memory array
US-2026038539-A1 · Feb 5, 2026 · US
This page is not indexed by search engines while we improve data quality.
Castro Hernan patents
Castro Hernan is listed as an inventor on 38 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Castro Hernan |
| Total patents | 38 |
| First publication | Feb 10, 2015 |
| Latest publication | Feb 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Programming memory cells based on context in a memory array
US-2026038582-A1 · Feb 5, 2026 · US
Nand memory array biasing for matrix vector multiplication
US-2026031152-A1 · Jan 29, 2026 · US
Three-dimensional ferroelectric tunnel junction device for multiply-accumulate operations
US-2026033252-A1 · Jan 29, 2026 · US
Memory device performing multiplication using logical states of memory cells
US-2025391472-A1 · Dec 25, 2025 · US
Memory device performing multiplication using logical states of memory cells
US-12437810-B2 · Oct 7, 2025 · US
Three-Dimensional Phase-Change Memory Array Operable to Perform Multiplication Accumulation Operations
US-2025272058-A1 · Aug 28, 2025 · US
Buried lines and related fabrication techniques
US-2025072118-A1 · Feb 27, 2025 · US
Truncated Resolution for Time Sliced Computation of Multiplication and Accumulation using a Memory Cell Array
US-2025061930-A1 · Feb 20, 2025 · US
Three-dimensional nor memory device for multiply-accumulate operations
US-2025029659-A1 · Jan 23, 2025 · US
Recent patents
Latest publications not already listed above.
Memory device using multi-pillar memory cells for matrix vector multiplication
US-2025014648-A1 · Jan 9, 2025 · US
Memory device for signed multi-bit to multi-bit multiplications
US-2024304254-A1 · Sep 12, 2024 · US
Memory device for multiplication using memory cells with different thresholds based on bit significance
US-2024304255-A1 · Sep 12, 2024 · US
Memory device performing signed multiplication using sets of two memory cells
US-2024303296-A1 · Sep 12, 2024 · US
Memory device performing signed multiplication using logical states of memory cells
US-2024304252-A1 · Sep 12, 2024 · US
Memory device for multiplication using memory cells having different bias levels based on bit significance
US-2024303039-A1 · Sep 12, 2024 · US
Memory device for summation of outputs of signed multiplications
US-2024304253-A1 · Sep 12, 2024 · US
Memory device having bonded integrated circuit dies used for multiplication
US-2024303037-A1 · Sep 12, 2024 · US
Memory device performing signed multiplication using sets of four memory cells
US-2024303038-A1 · Sep 12, 2024 · US
Memory device performing multiplication using logical states of memory cells
US-2024177772-A1 · May 30, 2024 · US
Buried lines and related fabrication techniques
US-2020323083-A1 · Oct 8, 2020 · US
Apparatuses and methods for efficient write in a cross-point array
US-10460802-B2 · Oct 29, 2019 · US
Apparatuses and methods for efficient write in a cross-point array
US-2018374537-A1 · Dec 27, 2018 · US
Apparatuses and methods for efficient write in a cross-point array
US-10083752-B2 · Sep 25, 2018 · US
Apparatuses and methods for efficient write in a cross-point array
US-2017358353-A1 · Dec 14, 2017 · US
Apparatuses and methods for efficient write in a cross-point array
US-9779811-B2 · Oct 3, 2017 · US
Apparatuses, devices and methods for sensing a snapback event in a circuit
US-9747981-B2 · Aug 29, 2017 · US
Apparatuses and methods for efficient write in a cross-point array
US-2017047118-A1 · Feb 16, 2017 · US
Apparatuses, devices and methods for sensing a snapback event in a circuit
US-2016365141-A1 · Dec 15, 2016 · US
Apparatuses and methods for efficient write in a cross-point array
US-9418738-B2 · Aug 16, 2016 · US
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.