Breakpoints in neural network accelerator
US-12210438-B1 · Jan 28, 2025 · US
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Borkovic Drazen patents
Borkovic Drazen is listed as an inventor on 38 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Borkovic Drazen |
| Total patents | 38 |
| First publication | May 19, 2015 |
| Latest publication | Jan 28, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Efficient utilization of processing element array
US-12198041-B2 · Jan 14, 2025 · US
Hierarchical partitioning of operators
US-12182688-B2 · Dec 31, 2024 · US
Using vector clocks to simplify a dependency graph in a neural network accelerator
US-12159217-B1 · Dec 3, 2024 · US
Vector clocks for highly concurrent execution engines
US-12106102-B1 · Oct 1, 2024 · US
Static memory allocation for neural network inference
US-12093806-B1 · Sep 17, 2024 · US
Reconfigurable neural network processing based on subgraph recognition
US-12045611-B1 · Jul 23, 2024 · US
DMA synchronization using alternating semaphores
US-11847507-B1 · Dec 19, 2023 · US
Efficient utilization of processing element array
US-2023359876-A1 · Nov 9, 2023 · US
Reconfigurable neural network processing based on subgraph recognition
US-11782706-B1 · Oct 10, 2023 · US
Recent patents
Latest publications not already listed above.
Vector clocks for highly concurrent execution engines
US-11775299-B1 · Oct 3, 2023 · US
Saving intermediate outputs of a neural network
US-11748622-B1 · Sep 5, 2023 · US
Efficient utilization of processing element array
US-11741350-B2 · Aug 29, 2023 · US
Time-based memory allocation for neural network inference
US-11610102-B1 · Mar 21, 2023 · US
Neural network operation reordering for parallel execution
US-11567778-B2 · Jan 31, 2023 · US
Allocation and placement of resources for network computation
US-11561833-B1 · Jan 24, 2023 · US
Configurable delay insertion in compiled instructions
US-11556342-B1 · Jan 17, 2023 · US
Breakpoints in neural network accelerator
US-11467946-B1 · Oct 11, 2022 · US
Event assignment for synchronization of concurrent execution engines
US-11442794-B1 · Sep 13, 2022 · US
Efficient race-condition detection
US-11354130-B1 · Jun 7, 2022 · US
Neural network layer-by-layer debugging
US-11308396-B2 · Apr 19, 2022 · US
Synchronization of DMA transfers for large number of queues
US-11221979-B1 · Jan 11, 2022 · US
Low latency neural network model loading
US-11182314-B1 · Nov 23, 2021 · US
Synchronization of concurrent computation engines
US-11175919-B1 · Nov 16, 2021 · US
Neural network operation reordering for parallel execution
US-2021247984-A1 · Aug 12, 2021 · US
Synchronization of concurrent computation engines
US-11061654-B1 · Jul 13, 2021 · US
Hierarchical partitioning of operators
US-2021158131-A1 · May 27, 2021 · US
Efficient utilization of processing element array
US-2021158132-A1 · May 27, 2021 · US
Neural network operation reordering for parallel execution
US-11016775-B2 · May 25, 2021 · US
Compile-time scheduling
US-11003429-B1 · May 11, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Amazon Tech Inc | 37 |
| Amazon Techaologies Inc | 1 |
| Synopsys Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06N3/063 | 31 |
| G06N3/0464 | 21 |
| G06N3/045 | 16 |
| G06N3/08 | 15 |
| G06N3/04 | 14 |