Method for fabricating a transistor with reduced junction leakage current
US-9368624-B2 · Jun 14, 2016 · US
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Patent family 51845730
This patent family groups 3 related publications across US. Members often share priority claims or equivalent filings in different countries.
| Field | Value |
|---|---|
| Family ID | 51845730 |
| Family type | — |
| Earliest priority | Dec 22, 2011 |
| First filing country | US |
| Member publications | 3 |
| Countries | US |
| Representative publication | US9368624B2 — Method for fabricating a transistor with reduced junction leakage current |
Representative publication
Best representative member for this family based on priority and filing country.
US9368624B2 — Method for fabricating a transistor with reduced junction leakage current (published Jun 14, 2016)
Member publications
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High uniformity screen and epitaxial layers for CMOS devices
US-9196727-B2 · Nov 24, 2015 · US
High Uniformity Screen and Epitaxial Layers for CMOS Devices
US-2015333144-A1 · Nov 19, 2015 · US