Control of instruction issue based on issue groups
US-2025208863-A1 · Jun 26, 2025 · US
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Microinstruction selection based on results of processing
Microinstruction selection based on results of processing · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F9/264 |
| Official title | {Microinstruction selection based on results of processing} |
| Display label | Microinstruction selection based on results of processing |
| Total patents | 14 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2017 | 1 |
| 2019 | 2 |
| 2020 | 2 |
| 2021 | 2 |
| 2022 | 1 |
| 2023 | 2 |
| 2024 | 1 |
| 2025 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Control of instruction issue based on issue groups
US-12340216-B1 · Jun 24, 2025 · US
Storing incidental branch predictions to reduce latency of misprediction recovery
US-12204908-B2 · Jan 21, 2025 · US
Computing chip and instruction processing method
US-2024419443-A1 · Dec 19, 2024 · US
Filtering micro-operations for a micro-operation cache in a processor
US-11726783-B2 · Aug 15, 2023 · US
Method for designing an application task architecture of an electronic control unit with one or more virtual cores
US-11709717-B2 · Jul 25, 2023 · US
Methods, systems, and apparatuses for a scalable reservation station implementing a single unified speculation state propagation and execution wakeup matrix circuit in a processor
US-2022206793-A1 · Jun 30, 2022 · US
Filtering Micro-Operations for a Micro-Operation Cache in a Processor
US-2021334098-A1 · Oct 28, 2021 · US
Memory device for updating micro-code, memory system including the memory device, and method for operating the memory device
US-10930350-B2 · Feb 23, 2021 · US
Method for designing an application task architecture of an electronic control unit with one or more virtual cores
US-2020371847-A1 · Nov 26, 2020 · US
Memory device, memory system including the memory device, and method for operating the memory device
US-2020202932-A1 · Jun 25, 2020 · US
Storing incidental branch predictions to reduce latency of misprediction recovery
US-2019369999-A1 · Dec 5, 2019 · US
Instructions for remote atomic operations
US-2019004810-A1 · Jan 3, 2019 · US
Hierarchical self-organizing classification processing in a network switch
US-9755947-B2 · Sep 5, 2017 · US