Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
US-10795823-B2 · Oct 6, 2020 · US
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Zimmerman David J patents
Zimmerman David J holds 8 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 8 |
| Recent patents | 0 |
| First publication | Aug 18, 2015 |
| Latest publication | Oct 6, 2020 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Apparatus and method for implementing a multi-level memory hierarchy
US-9600416-B2 · Mar 21, 2017 · US
Bad block management mechanism
US-9418700-B2 · Aug 16, 2016 · US
Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
US-9317429-B2 · Apr 19, 2016 · US
Adaptive configuration of non-volatile memory
US-9195589-B2 · Nov 24, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Dynamic partial power down of memory-side cache in a 2-level memory hierarchy
US-10795823-B2 · Oct 6, 2020 · US
Apparatus and method for implementing a multi-level memory hierarchy
US-9600416-B2 · Mar 21, 2017 · US
Bad block management mechanism
US-9418700-B2 · Aug 16, 2016 · US
Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
US-9317429-B2 · Apr 19, 2016 · US
Adaptive configuration of non-volatile memory
US-9195589-B2 · Nov 24, 2015 · US
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Physics | 8 |
| Cross-Sectional Technologies | 3 |