Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer
US-11581406-B2 · Feb 14, 2023 · US
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Daedalus Prime Llc patents
Daedalus Prime Llc holds 3 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 3 |
| Recent patents | 0 |
| First publication | Oct 18, 2022 |
| Latest publication | Feb 14, 2023 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Self-aligned gate edge and local interconnect
US-11563081-B2 · Jan 24, 2023 · US
Contact resistance reduction employing germanium overlayer pre-contact metalization
US-11476344-B2 · Oct 18, 2022 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer
US-11581406-B2 · Feb 14, 2023 · US
Self-aligned gate edge and local interconnect
US-11563081-B2 · Jan 24, 2023 · US
Contact resistance reduction employing germanium overlayer pre-contact metalization
US-11476344-B2 · Oct 18, 2022 · US
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 3 |